Low-Latency Bit-Accurate Architecture for Configurable Precision Floating-Point Division

Floating-point division is indispensable and becoming increasingly important in many modern applications. To improve speed performance of floating-point actual microprocessors, this paper proposes a low-latency architecture with multi-precision for which will meet the IEEE-754 standard. There are three parts design: pre-configuration, mantissa division, quotient normalization. In part based on fast algorithm, Predict–Correct algorithm employed brings about more partial bits per cycle without consuming too much circuit area. Detailed analysis presented to support guaranteed accuracy no restriction specific parameters. synthesis using TSMC, 90 nm standard cell library, results show that proposed has ≈63.6% latency, ≈30.23% total time (latency × period), ≈31.8% energy (power latency ≈44.6% efficient average period/efficient length) overhead over latest structure. terms faster than several classic processors.